The present invention relates to a semiconductor device having a multilevel wiring structure and, more particularly, to a semiconductor device having a Spin-on-Glass film (hereinafter referred to as an SOG film) employed as a part of an interlayer insulating film for a multilevel wiring structure.
A multilevel wiring technology reduces a wiring length and a parasitic capacitance between wirings, so that it is possible to achieve a high speed performance for a semiconductor device having a multilevel wiring structure. Furthermore, the multilevel wiring technology has an advantage in a reduction in freedom of layout designing, so that it is significantly effective for a high integration of a semiconductor element.
The multilevel wiring structure inevitably has an interlayer insulating film between lower and upper wiring lines to isolate them from each other. The desired one or ones of the metal wiring layers are connected electrically through an associated one of contact holes. The interlayer insulating film disposed between the metal wirings is flattened principally with the SOG film.
A conventional way to flatten the interlayer insulating film disposed between the multilayer metal wirings using the SOG film will be described with reference to the drawings below.
FIGS. 5(a) and 5(b) are drawings showing the flattening of the interlayer insulating film disposed between the multilevel metal wirings using the SOG film. Specifically, FIG. 5(a) is a plan view of the metal wirings of a large area used for such as a power source wiring and/or a GND wiring. FIG. 5(b) is a plan view of an array section.
FIGS. 6(a) to 6(d) are section views showing manufacturing steps, taken along the line A--A' of FIG. 5(a), and FIGS. 7(a) to 7(d) are section views showing manufacturing steps, taken along the line B--B' of FIG. 5(b).
The manufacturing steps for manufacturing the semiconductor device having the multilayer metal wirings will be described with reference to FIGS. 6(a) to 6(d) and FIGS. 7(a) to 7(d) below.
First, a metal wiring 102 is selectively formed on an insulating film 101. Then, an interlayer insulating film 103 formed of a silicon dioxide film is formed to cover the insulating film 101 and the metal wiring 102. Thereafter, to increase a grade of flatness of the interlayer insulating film disposed between the metal wirings, an SOG film 104 is coated on the entire surface of the interlayer insulating film 103 (FIG. 6(a) and FIG. 7(a)). At this time, a film thickness of the SOG film 104 formed on the metal wiring 102 is thicker as shown in FIGS. 6(a) and 7(a), as an area of the metal wiring 102 is wider. Specifically, in the region where the metal wiring 102 is formed as shown in FIG. 5(b), the SOG film 104 flows into a space between the metal wirings 102 during the formation of the SOG film 104 so that the film thickness of the portion of the SOG film 104 disposed on the metal wiring 102 is smaller. On the other hand, in case of the metal wiring 102 of a large area, there is no space for the SOG film 104 to flow into, so that the SOG film 104 is formed so as to have a larger film thickness.
Subsequently, the resultant structure is subjected to an anisotropic dry etching to leave respective parts of the SOG film 104 corresponding to surface steps of the metal wiring 102 (FIGS. 6(b) and 7(b)). In order to further flatten the uneven surface, another SOG film 105 is formed newly on the entire surface, and an anisotropic etching is performed, thereby increasing the degree of the flatness of the interlayer insulating film 103 (FIGS. 6(c) and 7(c)).
Thereafter, an interlayer insulating film 106 formed of a silicon dioxide film is formed, and contact holes 107 and metal wirings 108 are then formed (FIGS. 6(d) and 7(d)).
In this device, however, since the additional SOG film 105 is required to be formed and an anisotropic etching is performed to increase the degree of the flatness of the interlayer insulating film, the number of manufacturing steps is increased. Moreover, the dry etching is performed twice, so that the film thickness of the interlayer insulating film 103 becomes small to deteriorate the moisture resistant property thereof.
In addition, since on the metal wiring of a large area, the thicker SOG film is formed, the interlayer insulating film is not almost removed on the anisotropic dry etching. Consequently, an aspect ratio of the contact hole formed on the metal wiring of a large area is large. A reduction in step coverage of an upper wiring is produced, which is formed of i.e., aluminum disposed in the contact hole. Thus, an increase in contact hole resistance and a reduction in electromigration resistance property are produced.